1. Field of the Invention
The present invention relates to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory cell and a method for fabricating the same.
2. Description of Related Art
Since a nonvolatile memory device maintains data stored in memory cells even when power to the device is turned off, it is used in various applications and its importance is also increasing. As representative nonvolatile memory devices, a flash memory device and an electrical erasable programmable read only memory (EEPROM) device are well known.
A cell of the nonvolatile memory device, i.e., a nonvolatile memory cell, may be classified into a split gate structure and a stack gate structure spoken as electrically tunneling oxide (ETOX). The stack gate structure includes a stack structure where a floating gate and a control gate are sequentially stacked. The split gate structure is constructed of a floating gate and a structure that has one portion overlapping with the floating gate and the other portion horizontally disposed along a surface of a substrate.
FIG. 1 illustrates a cross-sectional view of a nonvolatile memory cell including the stack gate structure according to the prior art.
Referring to FIG. 1, the conventional nonvolatile memory cell includes a gate constructed of a stack structure. That is, a tunnel insulation layer 12, a floating gate 14, a dielectric layer 16 and a control gate 18 are sequentially formed over a substrate 10. In addition, a drain region 20 and a source region 22 are formed in portions of the substrate 10 that are aligned with and exposed at both sides of the control gate 18.
This stack gate is being widely used by its simple construction and the simplicity of fabricating processes. Specially, it is widely used when fabricating high density products. However, the stack gate may induce several problems when implementing a complicated operation by its simple construction. To solve the problems, various design technologies or test technologies are required. Furthermore, an additional area is required to apply the technologies to the chip construction. Accordingly, in low density products, a small size of the memory cell may not be an advantage anymore.
FIG. 2 illustrate a cross-sectional view of a nonvolatile memory cell including the split gate structure according to the prior art.
Referring to FIG. 2, in the nonvolatile memory cell, a control gate 38 is formed on a dielectric layer 36 to partially overlap with the top and one sidewall of a floating gate 34. A tunnel insulation layer 32 and the floating gate 34 are sequentially stacked over a substrate 30. Moreover, a drain region 40 is aligned with one side of the control gate 38 and a source region 42 is aligned with one side of the floating gate 34, wherein the drain region 40 and the source region 42 are formed in portions of the substrate 30 that are exposed.
The split gate is widely used by its excellencies of the operational reliability although it is not appropriate for a high density memory device by its great cell size. For instance, since the split gate can prevent the over erase that is a problem of the stack structure, it is used in the low density products or embedded memory devices. The reason why the spit gate is able to prevent the over erase is that it can maintain a threshold voltage of a memory cell constantly.
As described above, in an aspect of the operational reliability, the split gate shows more excellent performance than the stack gate. However, since the size of a cell including the split gate is great, there are many difficulties to apply the split gate to the high density memory device. Therefore, it is required to provide a nonvolatile memory cell that is applicable to the high density memory device by stably securing the operational reliability and accomplishing high integration, and operable in low voltage by lowering a driving voltage.